Pixel array substrate and organic light-emitting diode display

ABSTRACT

A pixel array substrate includes a first substrate, pixel units, data lines, scan lines, constant voltage lines, a constant voltage source, a constant voltage pad, and a conductive pattern. The first substrate has pixel regions and a peripheral region surrounding the pixel regions. The conductive pattern includes conductive lines interlaced with each other to form a net and a conductive frame that surrounds and is electrically coupled to the conductive lines. The conductive frame is in electrical contact with the constant voltage pad within the peripheral region. Each pixel region is defined by two adjacent scan lines and two adjacent data lines. A portion of one of the constant voltage lines located completely within each of the pixel regions is in electrical contact with one of the conductive lines within the pixel region. An OLED display including the pixel array substrate and another OLED are also provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. application Ser.No. 15/047,649, filed on Feb. 19, 2016, now allowed. The prior U.S.application Ser. No. 15/047,649 is a divisional application of U.S.application Ser. No. 14/133,653, filed on Dec. 19, 2013, now abandoned,which claims the priority benefit of Taiwan application serial no.102140462, filed on Nov. 7, 2013. The entirety of each of theabove-mentioned patent applications is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND OF THE INVENTION Field of the Invention

The invention relates to a pixel array substrate and a display, and moreparticularly to a pixel array substrate applicable to an organiclight-emitting diode (OLED) display and an OLED display.

Description of Related Art

At present, displays are categorized into plasma displays, liquidcrystal displays (LCD), inorganic electroluminescent displays, organiclight-emitting diode (OLED) displays, field emission displays (FED),electro-chromic displays, and so forth. Compared with other types ofdisplays, the OLED display has potential to become the mainstream in thenext generation, for it has the advantages of self-luminescence, noviewing angle dependence, low power consumption, wide range of workingtemperature, fast response speed, full-color display, etc.

A conventional OLED display includes a plurality of pixel unitsdistributed onto a substrate. Each of the pixel units includes a switchtransistor, a driver transistor electrically coupled to the switchtransistor, and a pixel electrode electrically coupled to the drivertransistor. A constant voltage line transmits a constant voltage to aninput electrode of the driver transistor of each pixel unit, such thatthe driver transistor is allowed to work in an amplification region.When the driver transistor stably works in the amplification region, thedriver transistor is able to provide constant current to an OLED layer,and thereby each pixel unit is able to display images with properbrightness.

However, the distances from the pixel units distributed onto thesubstrate to a constant voltage source are inconsistent, thus leading tothe difference in resistances between the input electrodes of the drivertransistors and the constant voltage source. In this case, the constantvoltage respectively transmitted to the input electrodes of the drivertransistors may vary, and thereby the OLED display is not able todisplay images with favorable display quality.

From another perspective, in the conventional OLED display, a commonelectrode layer and a control electrode of the driver transistor maytogether constitute a pixel storage capacitor. Due to the excessivelylong distance between the common electrode layer and the controlelectrode of the driver transistor, the pixel storage capacitance islow, which poses a negative impact on the display effects of the OLEDdisplay.

SUMMARY OF THE INVENTION

The invention is directed to an organic light-emitting diode (OLED)display and a pixel array substrate capable of lessening the differencein resistances between input electrodes of driver transistors and aconstant voltage source and further guaranteeing the favorable displaycapacity.

The invention is further directed to another OLED display capable ofincreasing pixel storage capacitance and further achieving satisfactorydisplay effects.

In an embodiment of the invention, a pixel array substrate that includesa first substrate, a plurality of pixel units, a plurality of datalines, a plurality of scan lines, a plurality of constant voltage lines,a constant voltage source, a constant voltage pad, and a conductivepattern is provided. The first substrate has a plurality of pixelregions arranged in an array and a peripheral region surrounding thepixel regions. The pixel units are located in the pixel regions. Each ofthe pixel units includes a switch transistor, a driver transistor, and apixel electrode. The switch transistor has an input electrode, a controlelectrode, and an output electrode; the driver transistor has an inputelectrode, a control electrode, and an output electrode. The outputelectrode of the switch transistor is electrically coupled to thecontrol electrode of the driver transistor. The pixel electrode iselectrically coupled to the output electrode of the driver transistor.The data lines are located on the first substrate and electricallycoupled to the input electrodes of the switch transistors. The scanlines are located on the first substrate, interlaced with the datalines, and electrically coupled to the control electrodes of the switchtransistors. The constant voltage lines are located on the firstsubstrate and electrically coupled to the input electrodes of the drivertransistors. The constant voltage source is located on the peripheralregion of the first substrate and provides a constant voltage to theconstant voltage lines. The constant voltage pad is located on theperipheral region of the first substrate and outputs the constantvoltage. The conductive pattern is located on the first substrate. Here,the conductive pattern includes a plurality of conductive lines and aconductive frame. The conductive lines are interlaced with each other toform a net and located on the pixel regions of the first substrate. Theconductive frame is located on the peripheral region of the firstsubstrate. Here, the conductive frame surrounds and is electricallycoupled to the conductive lines. The conductive frame is in electricalcontact with the constant voltage pad within the peripheral region. Eachof the pixel regions is defined by two adjacent scan lines and twoadjacent data lines. Besides, each of the pixel regions covers at leastone of the pixel units and a portion of one of the constant voltagelines. The covered portion of the one of the constant voltage linescompletely within each of the pixel regions is located in the each ofthe pixel regions and is in electrical contact with one of theconductive lines of the conductive pattern.

In an embodiment of the invention, an OLED display that includes theaforesaid pixel array substrate, a second substrate opposite to thefirst substrate, an OLED layer located between the pixel electrodes andthe second substrate, and a common electrode layer located between thesecond substrate and the OLED layer is provided.

In an embodiment of the invention, an OLED display that includes a pixelarray substrate, a second substrate opposite to a first substrate, anOLED layer located between pixel electrodes and the second substrate,and a common electrode layer located between the second substrate andthe OLED layer is provided. The pixel array substrate includes a firstsubstrate, a plurality of pixel units, a plurality of data lines, aplurality of scan lines, a plurality of constant voltage lines, aconstant voltage source, and a conductive pattern. The first substratehas a plurality of pixel regions arranged in an array and a peripheralregion surrounding the pixel regions. The pixel units are located in thepixel regions. Each of the pixel units includes a switch transistor, adriver transistor, and a pixel electrode. The switch transistor has aninput electrode, a control electrode, and an output electrode; thedriver transistor has an input electrode, a control electrode, and anoutput electrode. The output electrode of the switch transistor iselectrically coupled to the control electrode of the driver transistor.The pixel electrode is electrically coupled to the output electrode ofthe driver transistor. The data lines are located on the first substrateand electrically coupled to the input electrodes of the switchtransistors. The scan lines are located on the first substrate andelectrically coupled to the control electrodes of the switchtransistors. The constant voltage lines are located on the firstsubstrate and electrically coupled to the input electrodes of the drivertransistors. The constant voltage source is located on the peripheralregion of the first substrate and provides a constant voltage to theconstant voltage lines. The conductive pattern is located on the firstsubstrate and overlapped with the control electrode of each of thedriver transistors. The common electrode layer is overlapped with thecontrol electrodes of the driver transistors. A film layer where thecontrol electrodes of the driver transistors are located are between thefirst substrate and a film layer where the input electrodes of thedriver transistors are located. The film layer where the inputelectrodes of the driver transistors are located are between a filmlayer where the conductive pattern is located and the film layer wherethe control electrodes of the driver transistors are located. The filmlayer where the conductive pattern is located is between the OLED layerand the film layer where the input electrodes of the driver transistorsare located. The conductive pattern is in electrical contact with thecommon electrode layer.

According to an embodiment of the invention, the conductive lines of theconductive pattern and the constant voltage lines are overlapped.

According to an embodiment of the invention, the conductive lines aredivided into a plurality of first conductive lines and a plurality ofsecond conductive lines, the first conductive lines are parallel toextension directions of the constant voltage lines, the secondconductive lines are interlaced with the first conductive lines, and theconstant voltage lines cover the first conductive lines.

According to an embodiment of the invention, the second conductive linesare overlapped with the control electrodes of the driver transistors andthe data lines.

According to an embodiment of the invention, the constant voltage linesis overlapped with the control electrode of the driver transistor of thepixel units, so as to constitute a first storage capacitor. Theconductive line is overlapped with the control electrode of the drivertransistor of the pixel units, so as to constitute a second storagecapacitor. The first storage capacitor and the second storage capacitorare connected in parallel to constitute a pixel storage capacitor of thepixel units.

According to an embodiment of the invention, the conductive pattern isin a film layer different from film layers where the output electrodesof the driver transistors, the input electrodes of the drivertransistors, the control electrodes of the driver transistors, and thepixel electrodes are located.

According to an embodiment of the invention, a film layer where thecontrol electrodes of the driver transistors are located are between thefirst substrate and a film layer where the input electrodes of thedriver transistors are located. The film layer where the inputelectrodes of the driver transistors are located is between a film layerwhere the conductive pattern is located and the film layer where thecontrol electrodes of the driver transistors are located.

According to an embodiment of the invention, a film layer where theconductive pattern is located is between the first substrate and a filmlayer where the input electrodes of the driver transistors are located.The film layer where the input electrodes of the driver transistors arelocated is between a film layer where the control electrodes of thedriver transistors are located and the film layer where the conductivepattern is located.

According to an embodiment of the invention, the pixel array substratefurther includes a plurality of light-shielding patterns. Thelight-shielding patterns respectively shield a plurality of channels ofthe switch transistors and a plurality of channels of the drivertransistors.

According to an embodiment of the invention, the common electrode layeris overlapped with the control electrode of the driver transistor of thepixel unit to constitute a first storage capacitor. A portion of theconductive lines is overlapped with the control electrode of the drivertransistor of the pixel unit to constitute a second storage capacitor.The first storage capacitor and the second storage capacitor areconnected in parallel to constitute a pixel storage capacitor of the oneof the pixel units.

According to an embodiment of the invention, the conductive patternincludes a plurality of conductive lines and a conductive frame. Theconductive lines are interlaced with each other to form a net andlocated on the pixel regions of the first substrate. The conductiveframe is located on the peripheral region of the first substrate. Here,the conductive frame surrounds and is electrically coupled to theconductive lines.

As discussed above, in the OLED display and the pixel array substrate ofthe OLED display described in an embodiment of the invention, thenet-shaped conductive pattern lessens the difference in resistancesbetween the constant voltage source and the input electrodes of thedriver transistors distributed onto the first substrate, and thereby theconstant voltage respectively transmitted into the input electrode ofeach driver transistor does not vary significantly. Thereby, theconventional issue of unfavorable display quality caused by thesignificant difference in resistances between the input electrodes ofthe driver transistors and the constant voltage source can be betterresolved.

Besides, in the OLED display provided in another embodiment of theinvention, through the conductive pattern that is in electrical contactwith the common electrode and is overlapped with the control electrodeof each pixel unit, the pixel storage capacitance of each pixel unit mayincrease, and thus the OLED display is able to accomplish favorabledisplay effects.

To make the above features and advantages of the invention morecomprehensible, several embodiments accompanied with drawings aredescribed in detail as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide further understanding,and are incorporated in and constitute a part of this specification. Thedrawings illustrate exemplary embodiments and, together with thedescription, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram illustrating a pixel array substrateaccording to a first embodiment of the invention.

FIG. 2 is a schematic diagram illustrating one of the pixel regions anda portion of the peripheral region in the pixel array substrateaccording to the first embodiment of the invention.

FIG. 3 illustrates film layers other than the film layer where theconductive pattern depicted in FIG. 2 is located.

FIG. 4 illustrates the film layer where the conductive pattern depictedin FIG. 2 is located.

FIG. 5 is a schematic cross-sectional diagram illustrating the pixelarray substrate depicted in FIG. 2 along sectional lines A-A′, B-B′,C-C′, and D-D′ according to the first embodiment of the invention.

FIG. 6 is a schematic cross-sectional diagram illustrating an organiclight-emitting diode (OLED) display according to the first embodiment ofthe invention.

FIG. 7 is a schematic diagram illustrating a pixel array substrateaccording to a second embodiment of the invention.

FIG. 8 is a schematic diagram illustrating one of the pixel regions anda portion of the peripheral region in the pixel array substrateaccording to the second embodiment of the invention.

FIG. 9 illustrates film layers other than the film layer where theconductive pattern depicted in FIG. 8 is located.

FIG. 10 illustrates the film layer where the conductive pattern depictedin FIG. 8 is located.

FIG. 11 is a schematic cross-sectional diagram illustrating the pixelarray substrate depicted in FIG. 8 along sectional lines A-A′, B-B′,C-C′, and D-D′ according to the second embodiment of the invention.

FIG. 12 is a schematic cross-sectional diagram illustrating an OLEDdisplay according to the second embodiment of the invention.

FIG. 13 is a schematic diagram illustrating a pixel array substrateaccording to a third embodiment of the invention.

FIG. 14 is a schematic diagram illustrating one of the pixel regions anda portion of the peripheral region in the pixel array substrateaccording to the third embodiment of the invention.

FIG. 15 illustrates film layers other than the film layer where theconductive pattern depicted in FIG. 14 is located.

FIG. 16 illustrates the film layer where the conductive pattern depictedin FIG. 14 is located.

FIG. 17 is a schematic cross-sectional diagram illustrating the pixelarray substrate depicted in FIG. 14 along sectional lines A-A′, B-B′,C-C′, and D-D′ according to the third embodiment of the invention.

FIG. 18 is a schematic cross-sectional diagram illustrating an OLEDdisplay according to the third embodiment of the invention.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS First Embodiment

FIG. 1 is a schematic diagram illustrating a pixel array substrateaccording to a first embodiment of the invention. With reference to FIG.1, according to the present embodiment, the pixel array substrate 100includes a first substrate 110, a plurality of pixel units 120, aplurality of data lines DL, a plurality of scan lines SL interlaced withthe data lines DL, a plurality of constant voltage lines VL, a constantvoltage source 130, and a constant voltage pad 132. The first substrate110 has a plurality of pixel regions 110 a arranged in an array and aperipheral region 110 b surrounding the pixel regions 110 a. Each of thepixel regions 110 a is defined by two adjacent scan lines SL and twoadjacent data lines DL. That is, each of the pixel regions 110 aincludes an area surrounded by two adjacent scan lines SL and twoadjacent data lines DL, a portion of the two scan lines SL adjacent tothe area, and a portion of the two data lines DL adjacent to the area.The pixel units 120 are located in the pixel regions 110 a. To bespecific, each of the pixel regions 110 a includes at least one of thepixel units 120. In the present embodiment, each of the pixel regions110 a may include two of the pixel units 120. However, the invention isnot limited thereto, and each of the pixel regions 110 a may merelyinclude one pixel unit 110 a according to another embodiment.

Each of the pixel units 120 includes a switch transistor STFT, a drivertransistor DTFT, and a pixel electrode PE. The switch transistor STFThas an input electrode Is, a control electrode Gs, and an outputelectrode Os; the driver transistor DTFT has an input electrode Id, acontrol electrode Gd, and an output electrode Od. In each of the pixelunits 120, the output electrode Os of the switch transistor STFT iselectrically coupled to the control electrode Gd of the drivertransistor DTFT, and the pixel electrode PE is electrically coupled tothe output electrode Od of the driver transistor DTFT. The data lines DLare located on the first substrate 110 and electrically coupled to theinput electrodes Is of the switch transistors STFT. The scan lines SLare located on the first substrate 110 and electrically coupled to thecontrol electrodes Gs of the switch transistors STFT. The constantvoltage lines VL are electrically coupled to the input electrodes Id ofthe driver transistors DTFT. In the present embodiment, extensiondirections of the data lines DL may be perpendicular to extensiondirections of the scan lines SL, and extension directions of theconstant voltage lines VL may be parallel to the extension directions ofthe data lines DL, for instance. However, the invention is not limitedthereto, and the data lines DL, the scan lines SL, and the constantvoltage lines VL may be arranged in another appropriate manner.

The constant voltage source 130 is located on the peripheral region 110b of the first substrate 110 and provides a constant voltage to theconstant voltage lines VL. The constant voltage pad 132 is located onthe peripheral region 110 b of the first substrate 110 and outputs theconstant voltage provided by the constant voltage source 130. In thepresent embodiment, the constant voltage pad 132 may be a conductivearticle separated from the constant voltage lines VL. However, theinvention is not limited thereto, and the constant voltage pad 132 inanother embodiment may refer to a portion of the constant voltage linesVL that is located in the peripheral region 110 b and extended towardthe constant voltage source 130.

The pixel array substrate 100 further includes a conductive pattern 140located on the first substrate 110. The conductive pattern 140 includesa plurality of conductive lines 142 interlaced with each other to form anet and located on the pixel regions 110 a and a conductive frame 144located in the peripheral region 110 b. The conductive frame 144surrounds and is electrically coupled to the conductive lines 142.Particularly, the conductive frame 144 may be in electrical contact withall of the conductive lines 142 and has the same electrical potential asthose of the conductive lines 142. In the present embodiment, theconductive lines 142 and the conductive frame 144 may be located in thesame film layer. However, the invention is not limited thereto.

It should not mentioned that the conductive frame 144 is in electricalcontact with the constant voltage pad 132 within the peripheral region110 b, and a portion of at least one of the constant voltage lines VLcompletely within each of the pixel regions 110 a is located in the eachof the pixel regions 110 a and is in electrical contact with at leastone of the conductive lines 142. In the present embodiment, each of thepixel regions 110 a covers one of first conductive lines 142 a and oneof second conductive lines 142 b which are interlaced with each other,and the covered portion of the at least one of the constant voltagelines VL completely within the each of the pixel regions 110 a may be inelectrical contact with the one of the first conductive lines 142 a, theone of the second conductive lines 142 b, or a combination thereof. Asshown in FIG. 1, the covered portion of one of the constant voltagelines VL completely within each of the pixel regions 110 a is inelectrical contact with one of the first conductive lines 142 a.However, the invention is not limited thereto, and the covered portionof one of the constant voltage lines VL completely within each of thepixel regions 110 a may also be in electrical contact with one of secondconductive lines 142 b or simultaneously in electrical contact with thefirst and second conductive lines 142 a and 142 b according to otherembodiments of the invention.

In view of said electrical connection, the net-shaped conductive pattern140 is able to lessen the difference in resistances between the constantvoltage source 130 and the input electrodes Id of the driver transistorsDTFT distributed onto the first substrate 110, and thereby the constantvoltage respectively transmitted into the input electrode Id of eachdriver transistor DTFT does not vary significantly. Thereby, theconventional issue of unfavorable display quality caused by thesignificant difference in resistances between the input electrodes ofthe driver transistors and the constant voltage source can be betterresolved.

FIG. 2 is a schematic diagram illustrating one of the pixel regions anda portion of the peripheral region in the pixel array substrateaccording to the first embodiment of the invention. The pixel region 110a shown in FIG. 2 corresponds to the pixel region 110 a surrounded bydotted lines in FIG. 1, and the portion of the peripheral region 110Wshown in FIG. 2 corresponds to the peripheral region 110W surrounded bydotted lines in FIG. 1. FIG. 3 illustrates film layers other than thefilm layer where the conductive pattern depicted in FIG. 2 is located.FIG. 4 illustrates the film layer where the conductive pattern depictedin FIG. 2 is located. Note that FIG. 1 serves to explain the electricalconnection among the components in the pixel array substrate, while thedetailed structures of these components in the pixel array substrate areshown in FIG. 2, FIG. 3, and FIG. 4. The structures of these componentsin the pixel array will be elaborated hereinafter with reference to FIG.2, FIG. 3, and FIG. 4.

As shown in FIG. 2, FIG. 3, and FIG. 4, in the present embodiment, theconductive lines 142 of the conductive pattern 140 and the constantvoltage lines VL are overlapped. Specifically, the conductive lines 142are divided into a plurality of first conductive lines 142 a and aplurality of second conductive lines 142 b, the first conductive lines142 a are parallel to extension directions d of the constant voltagelines VL, and the second conductive lines 142 b are interlaced with thefirst conductive lines 142 a. The constant voltage lines VL cover thefirst conductive lines 142 a. The second conductive lines 142 b may beoverlapped with the control electrodes Gd of the driver transistors DTFTand the data lines DL. In brief, the area occupied by the conductivepattern 140 is mostly overlapped with the constant voltage lines VL andthe control electrodes Gd of the driver transistors DTFT. Hence, whenthe aforesaid issue of unfavorable display quality is resolved by meansof the conductive pattern 140, the aperture of the pixel array substrate100 is not negatively affected to an excessive degree.

In the present embodiment, the constant voltage line VL is overlappedwith the control electrode Gd of the driver transistor DTFT of the pixelunit 120, so as to constitute a first storage capacitor CS1, which isshown in FIG. 5. One of the conductive lines 142 of the conductivepattern 140 is overlapped with the control electrode Gd of the drivertransistor DTFT of the pixel unit 120, so as to constitute a secondstorage capacitor CS2, which is shown in FIG. 5 as well. The firststorage capacitor CS1 and the second storage capacitor CS2 share thesame capacitor electrode (i.e., the control electrode Gd of the drivertransistor DTFT), and another capacitor electrode (i.e., the constantvoltage line VL) of the first storage capacitor CS1 and anothercapacitor electrode (i.e., the conductive line 142) of the secondstorage capacitor CS2 have the same electrical potential. Therefore, thefirst storage capacitor CS1 and the second storage capacitor CS2 areconnected in parallel to constitute a pixel storage capacitor of one ofthe pixel units 120. That is, the pixel storage capacitance of the pixelunit 120 is obtained by adding the first storage capacitance and thesecond storage capacitance. Thereby, the conductive pattern 140 (i.e.,the capacitor electrode of the second storage capacitor) not only canresolve said issue of unfavorable display quality but also can increasethe pixel storage capacitance of the pixel unit 120, such that the pixelarray substrate 100 may have the improved performance.

FIG. 5 is a schematic cross-sectional diagram illustrating a pixel arraysubstrate according to a first embodiment of the invention.Particularly, FIG. 5 corresponds to the sectional lines A-A′, B-B′ C-C′,and D-D′ depicted in FIG. 2. The relationship of the components in thepixel array will be elaborated hereinafter with reference to FIG. 2 andFIG. 5.

As shown in FIG. 2 and FIG. 5, in the present embodiment, the controlelectrodes Gd of the driver transistors DTFT, the control electrodes Gsof the switch transistors STFT, and the scan lines SL may be located inthe same film layer. The pixel array substrate 100 described hereinfurther includes an insulation layer GI (GI1) (shown in FIG. 5) thatcovers the control electrodes Gd and Gs and the scan lines SL. The filmlayers where the control electrodes Gd are located are between theinsulation layer GI (GI1) and the first substrate 110. The drivertransistors DTFT further include channels CHd that are overlapped withthe control electrodes Gd. The switch transistors STFT further includechannels CHs that are overlapped with the control electrodes Gs. Thechannels CHd of the driver transistors DTFT and the channels CHs of theswitch transistors STFT may be located in the same film layer. Theinsulation layer GI (GI1) may be located between the film layers wherethe channels CHd are located and the film layers where the controlelectrodes Gd are located.

In the present embodiment, the input electrodes Id and the outputelectrodes Od of the driver transistors DTFT, the input electrodes Isand the output electrodes Os of the switch transistors STFT, the datalines DL, the constant voltage lines VL, and the constant voltage pad132 may be located in the same film layer. The film layer where thechannels CHd of the driver transistors DTFT are located is between theinsulation layer GI1 and the film layer where the input electrodes Id ofthe driver transistors DTFT are located. However, the invention is notlimited thereto, and the constant voltage pad 132 and the controlelectrodes Gd of the driver transistors DTFT or other components may bein the same film layer according to other embodiments of the invention.

The pixel array substrate 100 described herein further includes aninsulation layer GI (GI2) (shown in FIG. 5) that covers the drivertransistors DTFT, the switch transistors STFT, the data lines DL, andthe constant voltage lines VL. The film layers where the inputelectrodes Id of the driver transistors DTFT are located are between theinsulation layer GI (GI2) and the film layer where channels CHd arelocated. In each of the pixel regions 110 a, a portion of the insulationlayer GI (GI2) has a plurality of openings H1 to H3. The opening H1 isfilled with the conductive lines 142 of the conductive pattern 140, suchthat the conductive lines 142 are in electrical contact with theconstant voltage lines VL. The opening H2 is filled with the pixelelectrode PE, such that the pixel electrode PE is in electrical contactwith the output electrode Od of the driver transistor DTFT. In theperipheral region 110 b, a portion of the insulation layer GI (GI2) hasthe opening H3. The opening H3 is filled with the conductive frame 144of the conductive pattern 140, such that the conductive frame 144 is inelectrical contact with the constant voltage pad 132 that outputs theconstant voltage.

According to the present embodiment, the conductive pattern 140 is inthe film layer different from the film layer where the output electrodesOd of the driver transistors DTFT, the input electrodes Id of the drivertransistors DTFT, the control electrodes Gd of the driver transistorsDTFT, and the pixel electrodes PE are located. Namely, the film layerwhere the insulation layer GI (GI2) is located may be between the filmlayer where the conductive pattern 140 is located and the film layerswhere the input electrodes Id of the driver transistors DTFT arelocated.

In the present embodiment, the pixel array substrate 100 furtherincludes light-shielding patterns 146. The light-shielding patterns 146respectively shield the channels CHs of the switch transistors STFT andthe channels CHd of the driver transistors DTFT. In the presentembodiment, the conductive frame 140 and the light-shielding patterns146 may be located in the same film layer. As shown in FIG. 5, thelight-shielding patterns 146 may shield the light beam L on top of thepixel electrode PE. That is, when the pixel array substrate 100 is apart of the OLED display, the light-shielding patterns 146 may shieldthe light beam from the OLED layer, and thereby the OLED display havingthe pixel array substrate 100 may have the improved performance.

The pixel array substrate 100 described herein further includes aninsulation layer GI (GI3) that covers the conductive pattern 140 and thelight-shielding patterns 146. The film layer where the conductivepattern 140 is located is between the insulation layer GI (GI3) and theinsulation layer GI (GI2). The insulation layer GI (GI3) is locatedbetween the film layers where the pixel electrodes PE are located andthe film layer where the conductive pattern 140 is located. The openingsH2 and H4 of the insulation layers GI (GI2) and GI (GI3) are filled withthe pixel electrodes PE, such that the pixel electrodes PE are inelectrical contact with the output electrodes Od of the drivertransistors DTFT.

In the present embodiment, the film layer where the control electrodesGd of the driver transistors DTFT is located are between the firstsubstrate 110 and the film layer where the input electrodes Id of thedriver transistors DTFT are located, and the film layer where the inputelectrodes Id of the driver transistors DTFT are located is between thefilm layer where the conductive pattern 140 is located and the filmlayer where the control electrodes Gd of the driver transistors DTFT arelocated. That is, the driver transistors DTFT described herein may bebottom-gate transistors. In the present embodiment, the film layerswhere the components of the switch transistors STFT are located are thesame as the film layers where the components of the driver transistorsDTFT are located, and the switch transistors STFT described herein maybe bottom-gate transistors as well. However, the invention is notlimited thereto, and the driver transistors DTFT and the switchtransistors STFT in other embodiments of the invention may be in anotherform.

FIG. 6 is a schematic cross-sectional diagram illustrating an OLEDdisplay according to the first embodiment of the invention. Withreference to FIG. 6, the OLED display 1000 includes the pixel arraysubstrate 100, a second substrate 200 opposite to the first substrate110, an OLED layer OLED located between the pixel electrodes PE and thesecond substrate 200, and a common electrode layer 300 located betweenthe second substrate 200 and the OLED layer OLED. Since the OLED display1000 employs the pixel array substrate 100, the OLED display 1000 isalso able to resolve the conventional issue of unfavorable displayquality caused by the significant difference in resistances between theinput electrodes of the driver transistors and the constant voltagesource.

Second Embodiment

FIG. 7 is a schematic diagram illustrating a pixel array substrateaccording to a second embodiment of the invention. With reference toFIG. 7, the pixel array substrate 100′ described in the presentembodiment is similar to the pixel array substrate 100 described in thefirst embodiment, and thus the same and corresponding components of thetwo pixel array substrates 100 and 100′ are represented by the same orcorresponding reference numbers. The difference between the pixel arraysubstrate 100′ and the pixel array substrate 100 lies in that the typesof the driver transistors DTFT′ and the switch transistors STFT′ of thepixel array substrate 100′ are different from those of the drivertransistors DTFT and the switch transistors STFT of the pixel arraysubstrate 100, and the relative relationship between the conductivepattern 140′ and other film layers is also different from that betweenthe conductive pattern 140 and other film layers. Said difference willbe demonstrated below, while the similarity will not be furtherdescribed.

With reference to FIG. 7, similar to the pixel array substrate 100described in the first embodiment, the pixel array substrate 100′described herein includes a first substrate 110, a plurality of pixelunits 120, a plurality of data lines DL, a plurality of scan lines SL, aplurality of constant voltage lines VL, a constant voltage source 130,and a constant voltage pad 132. The first substrate 110 has a pluralityof pixel regions 110 a arranged in an array and a peripheral region 110b surrounding the pixel regions 110 a. The pixel units 120 are locatedin the pixel regions 110 a. Each of the pixel units 120 includes aswitch transistor STFT, a driver transistor DTFT, and a pixel electrodePE. The switch transistor STFT has an input electrode Is, a controlelectrode Gs, and an output electrode Os; the driver transistor DTFT hasan input electrode Id, a control electrode Gd, and an output electrodeOd. The output electrode Os of the switch transistor STFT iselectrically coupled to the control electrode Gd of the drivertransistor DTFT. The pixel electrode PE is electrically coupled to theoutput electrode Od of the driver transistor DTFT. The data lines DL arelocated on the first substrate 110 and electrically coupled to the inputelectrodes Is of the switch transistors STFT. The scan lines SL arelocated on the first substrate 110, interlaced with the data lines DL,and electrically coupled to the control electrodes Gs of the switchtransistors STFT. The constant voltage lines VL are located on the firstsubstrate 110 and electrically coupled to the input electrodes Id of thedriver transistors DTFT. The constant voltage source 130 is located onthe peripheral region 110 b of the first substrate 110 and provides aconstant voltage to the constant voltage lines VL. The constant voltagepad 132 is located on the peripheral region 110 b of the first substrate110 and outputs the constant voltage provided by the constant voltagesource 130.

The pixel array substrate 100′ also includes a conductive pattern 140′located on the first substrate 110. The conductive pattern 140′ includesa plurality of conductive lines 142′ interlaced with each other to forma net and located on the pixel regions 110 a and a conductive frame 144′located in the peripheral region 110 b. The conductive frame 144′surrounds and is electrically coupled to all of the conductive lines142′. The conductive frame 144′ is in electrical contact with theconstant voltage pad 132 within the peripheral region 110 b. Each of thepixel regions 110 a is defined by two adjacent scan lines SL and twoadjacent data lines DL. Besides, each of the pixel regions 110 a coversat least one of the pixel units 120 and a portion of at least one of theconstant voltage lines VL. The covered portion of the at least one ofthe constant voltage lines VL located completely within each of thepixel regions 110 a is in electrical contact with at least one of theconductive lines 142′ within the pixel region 110 a.

FIG. 8 is a schematic diagram illustrating one of the pixel regions anda portion of the peripheral region in the pixel array substrateaccording to the second embodiment of the invention. The pixel region110 a shown in FIG. 8 corresponds to the pixel region 110 a surroundedby dotted lines in FIG. 7, and the portion of the peripheral region 110b′ shown in FIG. 8 corresponds to the peripheral region 110 b′surrounded by dotted lines in FIG. 1. FIG. 9 illustrates film layersother than the film layer where the conductive pattern depicted in FIG.8 is located. FIG. 10 illustrates the film layer where the conductivepattern depicted in FIG. 8 is located. FIG. 11 is a schematiccross-sectional diagram illustrating a pixel array substrate accordingto a second embodiment of the invention. Particularly, FIG. 11corresponds to the sectional lines A-A′, B-B′ C-C′, and D-D′ depicted inFIG. 8. Note that FIG. 7 serves to explain the electrical connectionamong the components in the pixel array substrate, while the detailedstructures of these components in the pixel array substrate are shown inFIG. 8, FIG. 9, and FIG. 10. The structures of these components in thepixel array will be elaborated hereinafter with reference to FIG. 8,FIG. 9, FIG. 10, and FIG. 11.

The difference between the first embodiment and the present embodimentlies in that the film layer where the conductive pattern 140′ is locatedis between the first substrate 110 and the film layer where the inputelectrodes Id of the driver transistors DTFT′ are located, and the filmlayer where the input electrodes Id of the driver transistors DTFT′ arelocated is between the film layer where the conductive pattern 140′ islocated and the film layer where the control electrodes Gd of the drivertransistors DTFT′ are located. That is, the driver transistors DTFT′described herein may be top-gate transistors. In the present embodiment,the film layers where the components of the switch transistors STFT′ arelocated are the same as the film layers where the components of thedriver transistors DTFT′ are located, and the switch transistors STFT′described herein may be top-gate transistors as well.

FIG. 12 is a schematic cross-sectional diagram illustrating an OLEDdisplay according to the second embodiment of the invention. Withreference to FIG. 12, the OLED display 1000′ includes the pixel arraysubstrate 100′, a second substrate 200 opposite to the first substrate110, an OLED layer OLED located between the pixel electrodes PE and thesecond substrate 200, and a common electrode layer 300 located betweenthe second substrate 200 and the OLED layer OLED. Since the effects andadvantages of the OLED display 1000′ and the pixel array substrate 100′are similar to those of the OLED display 1000 and the pixel arraysubstrate 100, no further description is provided hereinafter.

Third Embodiment

FIG. 13 is a schematic diagram illustrating a pixel array substrateaccording to a third embodiment of the invention. FIG. 14 is a schematicdiagram illustrating one of the pixel regions and a portion of theperipheral region in the pixel array substrate according to the thirdembodiment of the invention. The pixel region 110 a shown in FIG. 14corresponds to the pixel region 110 a surrounded by dotted lines in FIG.13, and the portion of the peripheral region 110W shown in FIG. 14corresponds to the peripheral region 11011′ surrounded by dotted linesin FIG. 13. FIG. 15 illustrates film layers other than the film layerwhere the conductive pattern depicted in FIG. 14 is located. FIG. 16illustrates the film layer where the conductive pattern depicted in FIG.14 is located. FIG. 17 is a schematic cross-sectional diagramillustrating a pixel array substrate according to a third embodiment ofthe invention. Particularly, FIG. 17 corresponds to the sectional linesA-A′, B-B′ C-C′, and D-D′ depicted in FIG. 14. Note that FIG. 13 servesto explain the electrical connection among the components in the pixelarray substrate, while the detailed structures of these components inthe pixel array substrate are shown in FIG. 14, FIG. 15, FIG. 16, andFIG. 17.

With reference to FIG. 13, FIG. 14, FIG. 15, FIG. 16, and FIG. 17, thepixel array substrate 100A described in the present embodiment issimilar to the pixel array substrate 100 described in the firstembodiment, and thus the same and corresponding components of the twopixel array substrates 100 and 100A are represented by the same orcorresponding reference numbers. The difference between the two pixelarray substrates 100 and 100A lies in that the conductive pattern 140Ais electrically insulated from the constant voltage lines VL in thepixel array substrate 100A. Said difference will be demonstrated below,while the similarity will not be further described.

The pixel array substrate 100A described in the present embodimentincludes a first substrate 110, a plurality of pixel units 120 locatedon the first substrate 110, a plurality of data lines DL located on thefirst substrate 110, a plurality of scan lines SL located on the firstsubstrate 110 and interlaced with the data lines DL, a plurality ofconstant voltage lines VL located on the first substrate 110 andinterlaced with the scan lines SL, a constant voltage source 130 locatedon the peripheral region 110 b of the first substrate 110, and theconductive pattern 140A. The constant voltage source 130 provides aconstant voltage to the constant voltage lines VL.

The first substrate 110 has a plurality of pixel regions 110 a arrangedin an array and a peripheral region 110 b surrounding the pixel regions110 a. The pixel units 120 are located in the pixel regions 110 a. Eachof the pixel regions 110 a is defined by two adjacent scan lines SL andtwo adjacent data lines DL interlaced with the two scan lines SL. Thepixel units 120 are located in the pixel regions 110 a. Each of thepixel regions 110 a includes at least one of the pixel units 120. Eachof the pixel units 120 includes a switch transistor STFT, a drivertransistor DTFT, and a pixel electrode PE. The switch transistor STFThas an input electrode Is, a control electrode Gs, and an outputelectrode Os; the driver transistor DTFT has an input electrode Id, acontrol electrode Gd, and an output electrode Od. The output electrodeOs of the switch transistor STFT is electrically coupled to the controlelectrode Gd of the driver transistor DTFT. The pixel electrode PE iselectrically coupled to the output electrode Od of the driver transistorDTFT. The data lines DL are electrically coupled to the input electrodesIs of the switch transistors STFT. The scan lines SL are electricallycoupled to the control electrodes Gs of the switch transistors STFT. Theconstant voltage lines VL are electrically coupled to the inputelectrodes Id of the driver transistors DTFT.

The conductive pattern 140A is similar to the conductive pattern 140described in the first embodiment. Specifically, from the directionperpendicular to the first substrate 110, it can be observed that therelative positions of the conductive pattern 140A and other componentsof the pixel array substrate 100A are the same as those of theconductive pattern 140 and other components of the pixel array substrate100. The film layers where the conductive pattern 140A and othercomponents of the pixel array substrate 100A are located and the filmlayers where the conductive pattern 140 and other components of thepixel array substrate 100 are located are arranged in the same order.The difference between the conductive pattern 140A and the conductivepattern 140 lies in that the conductive pattern 140A is not inelectrical contact with the constant voltage lines VL, while theconductive pattern 140 is in electrical contact with the constantvoltage lines VL. Specifically, the conductive pattern 140A alsoincludes a plurality of conductive lines 142A and a conductive frame144A. The difference between the conductive frame 144A described in thepresent embodiment and the conductive frame 144 described in the firstembodiment lies in that the conductive frame 144A is not electricallyconnected to the constant voltage lines VL nor electrically connected tothe constant voltage source 130. The difference between the conductivelines 142A described in the present embodiment and the conductive lines142 described in the first embodiment lies in that the conductive lines142A are not electrically connected to the constant voltage lines VL norelectrically connected to the constant voltage source 130.

FIG. 18 is a schematic cross-sectional diagram illustrating an OLEDdisplay according to the third embodiment of the invention. Withreference to FIG. 18, the OLED display 1000A includes the pixel arraysubstrate 100A depicted in FIG. 17, a second substrate 200 opposite tothe first substrate 110, an OLED layer OLED located between the pixelelectrodes PE and the second substrate 200, and a common electrode layer300A located between the second substrate 200 and the OLED layer OLED.

The common electrode layer 300A is overlapped with the controlelectrodes Gd of the driver transistors DTFT. The film layer where thecontrol electrode Gd of each of the driver transistors DTFT is locatedis between the first substrate 110 and the film layer where the inputelectrode Id of each of the driver transistors DTFT is located. The filmlayer where the input electrode Id of each driver transistor DTFT islocated is between a film layer where the conductive pattern 140A islocated and the film layer where the control electrode Gd of each drivertransistor DTFT is located. The film layer where the conductive pattern140A is located is between the OLED layer OLED and the film layer wherethe input electrode Id of each driver transistor DTFT is located.

It should be mentioned that the conductive pattern 140A is in electricalcontact with the common electrode layer 300A. The common electrode layer300A is overlapped with the control electrode Gd of the drivertransistor DTFT of one of the pixel units 120 to constitute a firststorage capacitor. A portion of the conductive pattern 140A isoverlapped with the control electrode Gd of the driver transistor DTFTof one of the pixel units 120 (shown in FIG. 14), so as to constitute asecond storage capacitor. The first storage capacitor and the secondstorage capacitor share the same capacitor electrode (i.e., the controlelectrode Gd of the driver transistor DTFT), and another capacitorelectrode (i.e., the common electrode layer 300) of the first storagecapacitor CS1 and another capacitor electrode (i.e., the conductivepattern 140A) of the second storage capacitor have the same electricalpotential. Therefore, the first storage capacitor and the second storagecapacitor are connected in parallel to constitute a pixel storagecapacitor of one of the pixel units 120. That is, the pixel storagecapacitance of the pixel unit 120 is obtained by adding the firststorage capacitance and the second storage capacitance. Due to theconductive pattern 140A (i.e., the capacitor electrode of the secondstorage capacitor), the pixel storage capacitance of the pixel unit 120can be enhanced, and thus the OLED display 1000A may achieve favorabledisplay effects. To be specific, the distance from the conductivepattern 140A to the control electrode Gd is less than the distance fromthe common electrode layer 300A to the control electrode Gd; therefore,the second storage capacitance generated by the conductive pattern 140Amay be greater than the first storage capacitance generated by thecommon electrode layer 300A, and thus the pixel storage capacitance issignificantly increased. As a result, the conventional issue ofinsufficient pixel storage capacitance caused by the excessively largedistance from the common electrode layer to the control electrode Gd canbe better resolved.

To sum up, in the OLED display and the pixel array substrate of the OLEDdisplay described in an embodiment of the invention, the net-shapedconductive pattern lessens the difference in resistances between theconstant voltage source and the input electrodes of the drivertransistors distributed onto the first substrate, and thereby theconstant voltage respectively transmitted into the input electrode ofeach driver transistor does not vary significantly. Thereby, theconventional issue of unfavorable display quality caused by thesignificant difference in resistances between the input electrodes ofthe driver transistors and the constant voltage source can be betterresolved.

Besides, in the OLED display provided in another embodiment of theinvention, through the conductive pattern that is in electrical contactwith the common electrode and is overlapped with the control electrodeof each pixel unit, the pixel storage capacitance of each pixel unit mayincrease, and thus the OLED display is able to accomplish favorabledisplay effects.

Although the invention has been described with reference to the aboveexemplary embodiments, it will be apparent to one of ordinary skill inthe art that modifications to the described exemplary embodiments may bemade without departing from the spirit of the invention. Accordingly,the scope of the invention will be defined by the attached claims andnot by the above detailed descriptions.

What is claimed is:
 1. A pixel array substrate comprising: a first substrate having a plurality of pixel regions arranged in an array and a peripheral region surrounding the pixel regions; a plurality of pixel units located in the pixel regions, each of the pixel units comprising: a switch transistor having an input electrode, a control electrode, and an output electrode; a driver transistor having an input electrode, a control electrode, and an output electrode, wherein the output electrode of the switch transistor is electrically coupled to the control electrode of the driver transistor; and a pixel electrode electrically coupled to the output electrode of the driver transistor; a plurality of data lines located on the first substrate and electrically coupled to the input electrodes of the switch transistors; a plurality of scan lines located on the first substrate, interlaced with the data lines, and electrically coupled to the control electrodes of the switch transistors; a plurality of constant voltage lines located on the first substrate and electrically coupled to the input electrodes of the driver transistors; a constant voltage source located on the peripheral region of the first substrate, the constant voltage source providing a constant voltage to the constant voltage lines; a constant voltage pad located on the peripheral region of the first substrate, the constant voltage pad outputting the constant voltage; and a conductive pattern located on the first substrate, the conductive pattern comprising: a plurality of conductive lines interlaced with each other to form a net and located on the pixel regions of the first substrate; and a conductive frame located on the peripheral region of the first substrate and surrounding and electrically coupled to the conductive lines, the conductive frame being in electrical contact with the constant voltage pad within the peripheral region, wherein each of the pixel regions is defined by two adjacent scan lines of the scan lines and two adjacent data lines of the data lines, at least one of the pixel units and a portion of one of the constant voltage lines are located within each of the pixel regions, the portion of the one of the constant voltage lines is in electrical contact with one of the conductive lines of the conductive pattern, the one of the conductive lines is completely located within the each of the pixel regions, and the conductive pattern is in a film layer different from film layers where the output electrodes of the driver transistors, the input electrodes of the driver transistors, the control electrodes of the driver transistors, and the pixel electrodes are located.
 2. The pixel array substrate as recited in claim 1, wherein the conductive lines of the conductive pattern and the constant voltage lines are overlapped.
 3. The pixel array substrate as recited in claim 2, wherein the conductive lines are divided into a plurality of first conductive lines and a plurality of second conductive lines, the first conductive lines are parallel to extension directions of the constant voltage lines, the second conductive lines are interlaced with the first conductive lines, and the constant voltage lines cover the first conductive lines.
 4. The pixel array substrate as recited in claim 3, wherein the second conductive lines are overlapped with the control electrodes of the driver transistors and the data lines.
 5. The pixel array substrate as recited in claim 1, wherein the one of the constant voltage lines is overlapped with the control electrode of the driver transistor of the one of the pixel units to constitute a first storage capacitor, the one of the conductive lines is overlapped with the control electrode of the driver transistor of the one of the pixel units to constitute a second storage capacitor, and the first storage capacitor and the second storage capacitor are connected in parallel to constitute a pixel storage capacitor of the one of the pixel units.
 6. The pixel array substrate as recited in claim 1, wherein a film layer where the conductive pattern is located is between the first substrate and a film layer where the input electrodes of the driver transistors are located, and the film layer where the input electrodes of the driver transistors are located is between a film layer where the control electrodes of the driver transistors are located and the film layer where the conductive pattern is located.
 7. The pixel array substrate as recited in claim 1, further comprising a plurality of light-shielding patterns respectively shielding a plurality of channels of the switch transistors and a plurality of channels of the driver transistors.
 8. The pixel array substrate as claimed in claim 7, wherein the light-shielding patterns and the conductive pattern are located in the same film layer. 